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• Library Declaration
DATA TYPES & OBJECTS IN VHDL
• Delta Delay
• Operators in VHDL
• Shift Operator
• Relational Operator
• Arithmetic Operator
• User-Defined Data Types
• Pre-Defined Data Types
DATA FLOW MODELING
• Keyword description of Dataflow Modeling.
• When else statement.
• With Select Statement.
• Process Keyword.
• Conditional Statements
• If else statement
• Case statement
• Loops in VHDL
• For Loop
• While Loop
• No Iteration Scheme Loop
• Sequential Circuits in Behavioral Modeling
• Combinational Circuits in Behavioral Modeling
• Logic Gates
• Signal Attribute
• Data Attribute
• User-Defined Attribute
• Pre-defined Package
• User-defined Package
• Sub programs.
• Local Function
• Pre-defined Function
• Local Procedure
• Pre-defined Procedure
• NULL Statement
• NEXT Statement
• EXIT Statement
• Benefits of Structural Modeling.
• Component Interfacing
• Port Mapping
FINITE STATE MACHINE
• Introduction to FINITE STATE MACHINE (FSM).
• Moore’s Machine.
• Mealy Machine.
• Counters (MOD-3, MOD-5, MOD-7)
• Flip Flops using FSM.
SHIFT REGISTERS & MEMORIES
• Memory Design
• Design of ALU
• Traffic Light Controller
• Single way
• Four way
• Design of Shift Unit
• Design of Comparator
• Booth Multiplier
• Wallance Tree Multiplier
• Introduction to FPGA.
• Introduction to CPLD.
• Brief Description of Hardware KIT.
• Working on Physical FPGA & CPLD.
• Interfacing of LED’s.
• Keypad Scanner
BEHAVIORAL MODELING ADVANCED TOPICS
• MEMORY DESIGN – RAM / ROM.
• CLOCK DIVIDER RTL
HARDWARE INTERFACING ADVANCED TOPICS
• 7 Segment interfacing.
• Counter on 7-Segment.
• LCD Interfacing.
• Test bench.
• Delays in VHDL.
• Generics & generic map.
• Guarded block.
• Operator overloading.
• Function overloading.
INDRODUCTION TO VERILOG HDL
• Needs of VERILOG HDL.
• Difference between Verilog HDL & VHDL.
• Application of Verilog HDL
• Market Need.
• TLC- 4 Road / 1 Way on FPGA / CPLD XILINX SPRTAN 3E.